1. Field of the Invention
The invention relates to analyzing printed image distortion, and in particular to a system and method of determining the impact of line end shortening in the production of integrated circuits.
2. Description of the Related Art
FIG. 1A illustrates a standard layout structure 100 for forming a transistor. Specifically, layout structure 100 includes a gate 101 and two diffusion areas 102, which form the source and drain of the transistor. A first portion of gate 101 that extends past diffusion areas 102 and then terminates without connection is defined as an endcap margin 103, whereas a second portion of gate 101 that extends past diffusion areas 102 and connects to other structures is defined as a fieldcap margin 104.
One form of image distortion is line end shortening, wherein a feature is less than its nominal length when a feature on a mask (or reticle) is transferred to a wafer. Line end shortening can be caused by diffraction, imperfect mask patterns (i.e. line rounding), resist, other processing effects, and/or combinations of one or more effects. FIG. 1B illustrates that line end shortening of gate 101 can cause an ideal printed line end 106, with endcap margin 103, to transfer to a wafer as actual printed line end 105. Note that actual endcap margin 107 of actual printed line end 105 is clearly less than endcap margin 103. Note further that line end shortening has greater effect on certain portions of the line end. Specifically, actual printed line end 105 also has rounded corners due to other optical effects. Thus, the impact of line end shortening is accentuated on the edges of gate 101 that will interface with diffusion areas 102 during operation of the transistor formed by gate 101 and diffusion areas 102.
The rounded corners of a gate can adversely impact transistor performance, as shown in FIG. 1C. For example, if an endcap margin 110 of a gate 108 is sufficiently small or the line end shortening is sufficiently great, then line end shortening (as indicated by actual printed line end 109) can decrease the flow of electrons between diffusion areas 111 when a predetermined voltage is applied to gate 108 (i.e. the transistor formed by gate 108 and diffusion areas 111 is turned “on”). Specifically, the corner rounding of actual printed line end 109 reduces the area over which electrons can travel. This corner rounding can also cause leakage currents in the transistor, thereby resulting in a defective device.
To solve such problems associated with line end shortening, design rules have been used that recommend minimum endcap margins in the layout. However, due to corner rounding variations and the assumption of worst-case scenarios, this endcap margin can be undesirably long, thereby reducing the silicon area available for other circuits.
FIG. 2A illustrates a method sometimes employed by wafer houses to measure the effect of line end shortening. For illustration purposes, the transistor formed by gate 101 and diffusion areas 102 (FIG. 1B) is shown relative to another transistor formed by a gate 101′ and diffusion areas 102′ (wherein these transistors substantially mirror each other). In this method, instead of measuring the total length of gates 101 and 101′, or their respective endcap margins (wherein either measurement can be inaccurate due to the corner rounding), the spacing between line ends is measured. For example, in the case of gates 101 and 101′, an ideal separation 201 can instead transfer to a wafer as an actual separation 202. However, even if actual separation 202 can be accurately determined, additional analysis is still required to determine the impact of the line end shortening.
Specifically, although actual separation 202 in FIG. 2A can be acceptable (i.e. resulting in no defective devices), the identical separation in another configuration can result in one or more defective devices. For example, FIG. 2B illustrates two transistors: one transistor formed from gate 101 and diffusion areas 102 and another transistor formed from gate 108 and diffusion areas 107. Note that the measured distance between gates 101 and 108 (i.e. ideal separation 201) and the measured distance between actual printed line ends 105 and 109 (i.e. actual separation 202) are identical to those in FIG. 2A. However, in FIG. 2B, line end shortening can impact the functioning of the transistor formed by gate 108 and diffusion areas 107, but not the transistor formed by gate 101 and diffusion areas 102. Thus, an actual separation measurement cannot provide a reliable indication of the impact of line end shortening.
Therefore, a need arises for a method of accurately determining the impact of line end shortening.